PoC.xil.reconfig.icap_wrapper

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This module was designed to connect the Xilinx “Internal Configuration Access Port” (ICAP) to a PCIe endpoint on a Dini board. Tested on:

tbd

Entity Declaration:

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entity reconfig_icap_wrapper is
  generic (
    MIN_DEPTH_OUT     : positive := 256;
    MIN_DEPTH_IN      : positive := 256
  );
  port (
    clk       : in  std_logic;
    reset     : in  std_logic;
    clk_icap    : in  std_logic;    -- clock signal for ICAP, max 100 MHz (double check with manual)

    icap_busy   : out std_logic;    -- the ICAP is processing the data
    icap_readback : out std_logic;    -- high during a readback
    icap_partial_res: out std_logic;    -- high during reconfiguration

    -- data in
    write_put   : in  std_logic;
    write_full    : out std_logic;
    write_data    : in  std_logic_vector(31 downto 0);
    write_done    : in  std_logic;    -- high pulse/edge after all data was written

    -- data out
    read_got    : in  std_logic;
    read_valid    : out std_logic;
    read_data     : out std_logic_vector(31 downto 0)
  );
end reconfig_icap_wrapper;