This library is published and maintained by Chair for VLSI Design, Diagnostics
and Architecture - Faculty of Computer Science, Technische Universität Dresden,
Germany
https://tu-dresden.de/ing/informatik/ti/vlsi
The PoC-Library Documentation¶
PoC - “Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs.
All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and constants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a better hierachy.
Various simulation and synthesis tool chains are supported to interoperate with PoC. To generalize all supported free and commercial vendor tool chains, PoC is shipped with a Python based infrastructure to offer a command line based frontend.
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Cite the PoC-Library¶
The PoC-Library hosted at GitHub.com. Please use the following biblatex entry to cite us:
# BibLaTex example entry
@online{poc,
title={{PoC - Pile of Cores}},
author={{Chair of VLSI Design, Diagnostics and Architecture}},
organization={{Technische Universität Dresden}},
year={2016},
url={https://github.com/VLSI-EDA/PoC},
urldate={2016-10-28},
}
This document was generated on Mar 06, 2017 - 10:05.