PoC.xil.reconfig.icap_fsm

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This module parses the data stream to the Xilinx “Internal Configuration Access Port” (ICAP) primitives to generate control signals. Tested on:

  • Virtex-6
  • Virtex-7

Entity Declaration:

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entity reconfig_icap_fsm is
  port  (
    clk       : in  std_logic;
    reset     : in  std_logic;            -- high-active reset
    -- interface to connect to the icap
    icap_in     : out std_logic_vector(31 downto 0);  -- data that will go into the icap
    icap_out    : in  std_logic_vector(31 downto 0);  -- data from the icap
    icap_csb    : out std_logic;
    icap_rw     : out std_logic;

    -- data interface, no internal fifos
    in_data     : in  std_logic_vector(31 downto 0);  -- new configuration data
    in_data_valid : in  std_logic;            -- input data is valid
    in_data_rden  : out std_logic;            -- possible to send data
    out_data    : out std_logic_vector(31 downto 0);  -- data read from the fifo
    out_data_valid  : out std_logic;            -- data from icap is valid
    out_data_full : in  std_logic;            -- receiving buffer is full, halt icap

    -- control structures
    status      : out std_logic_vector(31 downto 0) -- status vector
  );
end reconfig_icap_fsm;