PoC.xil.ReconfiguratorΒΆ

GitHub Links

Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration Port (DRP) to reconfigure a primitive at runtime without reconfiguring the whole FPGA.

This module is a DRP master that can be pre-configured at compile time with different configuration sets. The configuration sets are mapped into a ROM. The user can select a stored configuration with ConfigSelect. Sending a strobe to Reconfig will start the reconfiguration process. The operation completes with another strobe on ReconfigDone.

Entity Declaration:

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
19
20
21
22
entity xil_Reconfigurator is
  generic (
    DEBUG           : boolean                   := FALSE;                                       --
    CLOCK_FREQ      : FREQ                      := 100 MHz;                                     --
    CONFIG_ROM      : in  T_XIL_DRP_CONFIG_ROM  := (0 downto 0 => C_XIL_DRP_CONFIG_SET_EMPTY)   --
  );
  port (
    Clock           : in  std_logic;
    Reset           : in  std_logic;

    Reconfig        : in  std_logic;                                                            --
    ReconfigDone    : out std_logic;                                                            --
    ConfigSelect    : in  std_logic_vector(log2ceilnz(CONFIG_ROM'length) - 1 downto 0);         --

    DRP_en          : out std_logic;                                                            --
    DRP_Address     : out T_XIL_DRP_ADDRESS;                                                    --
    DRP_we          : out std_logic;                                                            --
    DRP_DataIn      : in  T_XIL_DRP_DATA;                                                       --
    DRP_DataOut     : out T_XIL_DRP_DATA;                                                       --
    DRP_Ack         : in  std_logic                                                             --
  );
end entity;