This module synchronizes a vector of bits from clock-domain
Clock2. The clock-domain boundary crossing is done by a
change comparator, a T-FF, two synchronizer D-FFs and a reconstructive
XOR indicating a value change on the input. This changed signal is used
to capture the input for the new output. A busy flag is additionally
calculated for the input clock-domain. The output has strobe character
and is reset to it’s
INIT value after one clock cycle.
- This module uses sub modules which need to be constrained. Please attend to the notes of the instantiated sub modules.
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entity sync_Command is generic ( BITS : positive := 8; -- number of bit to be synchronized INIT : std_logic_vector := x"00000000"; -- SYNC_DEPTH : T_MISC_SYNC_DEPTH := T_MISC_SYNC_DEPTH'low -- generate SYNC_DEPTH many stages, at least 2 ); port ( Clock1 : in std_logic; -- <Clock> input clock Clock2 : in std_logic; -- <Clock> output clock Input : in std_logic_vector(BITS - 1 downto 0); -- @Clock1: input vector Output : out std_logic_vector(BITS - 1 downto 0); -- @Clock2: output vector Busy : out std_logic; -- @Clock1: busy bit Changed : out std_logic -- @Clock2: changed bit ); end entity;