This module synchronizes multiple high-active bits from clock-domain
Clock1 to clock-domain
Clock2. The clock-domain boundary crossing is
done by a T-FF, two synchronizer D-FFs and a reconstructive XOR. A busy
flag is additionally calculated and can be used to block new inputs. All
bits are independent from each other. Multiple consecutive strobes are
suppressed by a rising edge detection.
Use this synchronizer only for one-cycle high-active signals (strobes).
- This module uses sub modules which need to be constrained. Please attend to the notes of the instantiated sub modules.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
entity sync_Strobe is generic ( BITS : positive := 1; -- number of bit to be synchronized GATED_INPUT_BY_BUSY : boolean := TRUE; -- use gated input (by busy signal) SYNC_DEPTH : T_MISC_SYNC_DEPTH := T_MISC_SYNC_DEPTH'low -- generate SYNC_DEPTH many stages, at least 2 ); port ( Clock1 : in std_logic; -- <Clock> input clock domain Clock2 : in std_logic; -- <Clock> output clock domain Input : in std_logic_vector(BITS - 1 downto 0); -- @Clock1: input bits Output : out std_logic_vector(BITS - 1 downto 0); -- @Clock2: output bits Busy : out std_logic_vector(BITS - 1 downto 0) -- @Clock1: busy bits ); end entity;