PoC.misc.sync.Pulse¶

This module synchronizes multiple pulsed bits into the clock-domain Clock. The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits are independent from each other. If a known vendor like Altera or Xilinx are recognized, a vendor specific implementation is chosen.

Attention

Use this synchronizer for very short signals (pulse).

Constraints:

General:: Please add constraints for meta stability to all ‘_meta’ signals and timing ignore constraints to all ‘_async’ signals.
Xilinx:: In case of a Xilinx device, this module will instantiate the optimized module PoC.xil.sync.Pulse. Please attend to the notes of sync_Bits.vhdl.
Altera sdc file:: TODO

Entity Declaration:

entity sync_Pulse is
  generic (
    BITS          : positive            := 1;                       -- number of bit to be synchronized
    SYNC_DEPTH    : T_MISC_SYNC_DEPTH   := T_MISC_SYNC_DEPTH'low    -- generate SYNC_DEPTH many stages, at least 2
  );
  port (
    Clock         : in  std_logic;                                  -- <Clock>  output clock domain
    Input         : in  std_logic_vector(BITS - 1 downto 0);        -- @async:  input bits
    Output        : out std_logic_vector(BITS - 1 downto 0)         -- @Clock:  output bits
  );
end entity;