This module synchronizes an asynchronous reset signal to the clock
Input can be asserted and de-asserted at any time.
Output is asserted asynchronously and de-asserted synchronously
to the clock.
Use this synchronizer only to asynchronously reset your design. The ‘Output’ should be feed by global buffer to the destination FFs, so that, it reaches their reset inputs within one clock cycle.
- Please add constraints for meta stability to all ‘_meta’ signals and timing ignore constraints to all ‘_async’ signals.
- In case of a Xilinx device, this module will instantiate the optimized module xil_SyncReset. Please attend to the notes of xil_SyncReset.
- Altera sdc file:
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entity sync_Reset is generic ( SYNC_DEPTH : T_MISC_SYNC_DEPTH := T_MISC_SYNC_DEPTH'low -- generate SYNC_DEPTH many stages, at least 2 ); port ( Clock : in std_logic; -- <Clock> output clock domain Input : in std_logic; -- @async: reset input Output : out std_logic -- @Clock: reset output ); end entity;