PoC.io.uart.fifoΒΆ

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Small FIFO s are included in this module, if larger or asynchronous transmit / receive FIFOs are required, then they must be connected externally.

old comments:
UART BAUD rate generator bclk = bit clock is rising bclk_x8 = bit clock times 8 is rising

Entity Declaration:

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entity uart_fifo is
  generic (
    -- Communication Parameters
    CLOCK_FREQ              : FREQ;
    BAUDRATE                : BAUD;
    ADD_INPUT_SYNCHRONIZERS : boolean                       := TRUE;

    -- Buffer Dimensioning
    TX_MIN_DEPTH            : positive                      := 16;
    TX_ESTATE_BITS          : natural                       :=  0;
    RX_MIN_DEPTH            : positive                      := 16;
    RX_FSTATE_BITS          : natural                       :=  0;

    -- Flow Control
    FLOWCONTROL             : T_IO_UART_FLOWCONTROL_KIND    := UART_FLOWCONTROL_NONE;
    SWFC_XON_CHAR           : std_logic_vector(7 downto 0)  := x"11"; -- ^Q
    SWFC_XON_TRIGGER        : real                          := 0.0625;
    SWFC_XOFF_CHAR          : std_logic_vector(7 downto 0)  := x"13"; -- ^S
    SWFC_XOFF_TRIGGER       : real                          := 0.75
  );
  port (
    Clock         : in  std_logic;
    Reset         : in  std_logic;

    -- FIFO interface
    TX_put        : in  std_logic;
    TX_Data       : in  std_logic_vector(7 downto 0);
    TX_Full       : out std_logic;
    TX_EmptyState : out std_logic_vector(imax(0, TX_ESTATE_BITS-1) downto 0);

    RX_Valid      : out std_logic;
    RX_Data       : out std_logic_vector(7 downto 0);
    RX_got        : in  std_logic;
    RX_FullState  : out std_logic_vector(imax(0, RX_FSTATE_BITS-1) downto 0);
    RX_Overflow   : out std_logic;

    -- External pins
    UART_TX       : out std_logic;
    UART_RX       : in  std_logic;
    UART_RTS      : out std_logic;
    UART_CTS      : in  std_logic
  );
end entity;