PoC.mem.ocram.tdp_wf

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Inferring / instantiating true dual-port memory, with:

  • single clock, clock enable,
  • 2 read/write ports.

Command truth table:

ce we1 we2 Command
0 X X No operation
1 0 0 Read only from memory
1 0 1 Read from memory on port 1, write to memory on port 2
1 1 0 Write to memory on port 1, read from memory on port 2
1 1 1 Write to memory on both ports

Both reads and writes are synchronous to the clock.

The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:

Same-Port Read-During-Write

When writing data through port 1, the read output of the same port (q1) will output the new data (d1, in the following clock cycle) which is aka. “write-first behavior”.

Same applies to port 2.

Mixed-Port Read-During-Write
When reading at the write address, the read value will be the new data, aka. “write-first behavior”. Of course, the read is still synchronous, i.e, the latency is still one clock cyle.

If a write is issued on both ports to the same address, then the output of this unit and the content of the addressed memory cell are undefined.

For simulation, always our dedicated simulation model PoC.mem.ocram.tdp_sim is used.

Entity Declaration:

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entity ocram_tdp_wf is
  generic (
    A_BITS    : positive;                             -- number of address bits
    D_BITS    : positive;                             -- number of data bits
    FILENAME  : string    := ""                       -- file-name for RAM initialization
  );
  port (
    clk : in  std_logic;                              -- clock
    ce  : in  std_logic;                              -- clock-enable
    we1 : in  std_logic;                              -- write-enable for 1st port
    we2 : in  std_logic;                              -- write-enable for 2nd port
    a1   : in unsigned(A_BITS-1 downto 0);            -- address for 1st port
    a2   : in unsigned(A_BITS-1 downto 0);            -- address for 2nd port
    d1   : in std_logic_vector(D_BITS-1 downto 0);    -- write-data for 1st port
    d2   : in std_logic_vector(D_BITS-1 downto 0);    -- write-data for 2nd port
    q1   : out std_logic_vector(D_BITS-1 downto 0);   -- read-data from 1st port
    q2   : out std_logic_vector(D_BITS-1 downto 0)    -- read-data from 2nd port
  );
end entity;