PoC.mem.ocram.tdp_simΒΆ

GitHub Links

Simulation model for true dual-port memory, with:

  • dual clock, clock enable,
  • 2 read/write ports.

The interface matches that of the IP core PoC.mem.ocram.tdp. But the implementation there is restricted to the description supported by various synthesis compilers. The implementation here also simulates the correct Mixed-Port Read-During-Write Behavior and handles X propagation.

Entity Declaration:

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
19
20
21
entity ocram_tdp_sim is
  generic (
    A_BITS    : positive;                             -- number of address bits
    D_BITS    : positive;                             -- number of data bits
    FILENAME  : string    := ""                       -- file-name for RAM initialization
  );
  port (
    clk1 : in std_logic;                              -- clock for 1st port
    clk2 : in std_logic;                              -- clock for 2nd port
    ce1 : in  std_logic;                              -- clock-enable for 1st port
    ce2 : in  std_logic;                              -- clock-enable for 2nd port
    we1 : in  std_logic;                              -- write-enable for 1st port
    we2 : in  std_logic;                              -- write-enable for 2nd port
    a1   : in unsigned(A_BITS-1 downto 0);            -- address for 1st port
    a2   : in unsigned(A_BITS-1 downto 0);            -- address for 2nd port
    d1   : in std_logic_vector(D_BITS-1 downto 0);    -- write-data for 1st port
    d2   : in std_logic_vector(D_BITS-1 downto 0);    -- write-data for 2nd port
    q1   : out std_logic_vector(D_BITS-1 downto 0);   -- read-data from 1st port
    q2   : out std_logic_vector(D_BITS-1 downto 0)    -- read-data from 2nd port
  );
end entity;