Third Party Libraries¶
The PoC-Library is shiped with different third party libraries, which are
located in the
<PoCRoot>/lib/ folder. This document lists all these
libraries, their websites and licenses.
Cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
|Copyright:||Copyright © 2013, Potential Ventures Ltd., SolarFlare Communications Inc.|
|License:||Revised BSD License (local copy)|
Open Source VHDL Verification Methodology (OS-VVM) is an intelligent testbench methodology that allows mixing of “Intelligent Coverage” (coverage driven randomization) with directed, algorithmic, file based, and constrained random test approaches. The methodology can be adopted in part or in whole as needed. With OSVVM you can add advanced verification methodologies to your current testbench without having to learn a new language or throw out your existing testbench or testbench models.
|Copyright:||Copyright © 2012-2016 by SynthWorks Design Inc.|
|License:||Artistic License 2.0 (local copy)|
The Open Source UVVM (Universal VHDL Verification Methodology) - VVC (VHDL Verification Component) Framework for making structured VHDL testbenches for verification of FPGA. UVVM consists currently of: Utility Library, VVC Framework and Verification IPs (VIP) for various protocols.
For what do I need this VVC Framework?
The VVC Framework is a VHDL Verification Component system that allows multiple interfaces on a DUT to be stimulated/handled simultaneously in a very structured manner, and controlled by a very simple to understand software like a test sequencer. VVC Framework is unique as an open source VHDL approach to building a structured testbench architecture using Verification components and a simple protocol to access these. As an example a simple command like
uart_expect(UART_VVCT, my_data), or
axilite_write(AXILITE_VVCT, my_addr, my_data, my_message)
will automatically tell the respective VVC (for UART or AXI-Lite) to execute
axilite_write() BFM respectively.
|Copyright:||Copyright © 2016 by Bitvis AS|
|License:||The MIT License (local copy)|
VUnit is an open source unit testing framework for VHDL released under the terms of Mozilla Public License, v. 2.0. It features the functionality needed to realize continuous and automated testing of your VHDL code. VUnit doesn’t replace but rather complements traditional testing methodologies by supporting a “test early and often” approach through automation.
|Copyright:||Copyright © 2014-2016, Lars Asplund firstname.lastname@example.org|
|License:||Mozilla Public License, Version 2.0 (local copy)|