PoC.misc.gearbox.down_dc

GitHub Links

This module provides a downscaling gearbox with a dependent clock (dc) interface. It perfoems a ‘word’ to ‘byte’ splitting. The default order is LITTLE_ENDIAN (starting at byte(0)). Input “In_Data” is of clock domain “Clock1”; output “Out_Data” is of clock domain “Clock2”. Optional input and output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE).

Assertions:

  • Clock periods of Clock1 and Clock2 MUST be multiples of each other.
  • Clock1 and Clock2 MUST be phase aligned (related) to each other.

Entity Declaration:

 1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
entity gearbox_down_dc is
  generic (
    INPUT_BITS            : positive        := 32;                          -- input bits ('words')
    OUTPUT_BITS           : positive        := 8;                           -- output bits ('byte')
    OUTPUT_ORDER          : T_BIT_ORDER     := LSB_FIRST;                   -- LSB_FIRST: start at byte(0), MSB_FIRST: start at byte(n-1)
    ADD_INPUT_REGISTERS   : boolean         := FALSE;                       -- add input register @Clock1
    ADD_OUTPUT_REGISTERS  : boolean         := FALSE                        -- add output register @Clock2
  );
  port (
    Clock1                : in  std_logic;                                  -- input clock domain
    Clock2                : in  std_logic;                                  -- output clock domain
    In_Data               : in  std_logic_vector(INPUT_BITS - 1 downto 0);  -- input word
    Out_Data              : out std_logic_vector(OUTPUT_BITS - 1 downto 0)  -- output word
  );
end entity;