PoC.mem.sdram.ctrl_phy_s3esk

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Physical layer used by module sdram_ctrl_s3esk.

Instantiates input and output buffer components and adjusts the timing for the Spartan-3E Starter Kit Board.

Clock and Reset Signals

Port Description
clk Base clock for command and write data path.
clk_n clk phase shifted by 180 degrees.
clk90 clk phase shifted by 90 degrees.
clk90_n clk phase shifted by 270 degrees.
clk_fb (on PCB) Driven by external feedback (sd_ck_fb) of DDR-SDRAM clock (sd_ck_p). Actually unused, just referenced below.
clk_fb90 clk_fb phase shifted by 90 degrees.
clk_fb90_n clk_fb phase shifted by 270 degrees.
rst Reset for clk.
rst180 Reset for clk_n
rst90 Reset for clk90.
rst270 Reset for clk270.
rst_fb90 Reset for clk_fb90.
rst_fb90_n Reset for clk_fb90_n.

Operation

Command signals and write data are sampled with the rising edge of clk.

Read data is aligned with clk_fb90_n. Either process data in this clock domain, or connect a FIFO to transfer data into another clock domain of your choice. This FIFO should capable of storing at least one burst (size BL/2) + start of next burst (size 1).

Write and read enable (wren_nxt, rden_nxt) must be hold for:

  • 1 clock cycle if BL = 2,
  • 2 clock cycles if BL = 4, or
  • 4 clock cycles if BL = 8.

They must be first asserted with the read and write command. Proper delay is included in this unit.

The first word to write must be asserted with the write command. Proper delay is included in this unit.

The SDRAM clock is regenerated in this module. The following timing is chosen for minimum latency (should work up to 100 MHz):

  • rising_edge(clk90) triggers rising_edge(sd_ck_p),
  • rising_edge(clk90_n) triggers falling_edge(sd_ck_p).

XST options: Disable equivalent register removal.

Synchronous resets are used. Reset must be hold for at least two cycles.

Entity Declaration:

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entity sdram_ctrl_phy_s3esk is
  port (
    clk     : in std_logic;
    clk_n   : in std_logic;
    clk90   : in std_logic;
    clk90_n : in std_logic;
    rst     : in std_logic;
    rst90   : in std_logic;
    rst180  : in std_logic;
    rst270  : in std_logic;

    clk_fb90   : in std_logic;
    clk_fb90_n : in std_logic;
    rst_fb90   : in std_logic;
    rst_fb270  : in std_logic;

    sd_cke_nxt : in std_logic;
    sd_cs_nxt  : in std_logic;
    sd_ras_nxt : in std_logic;
    sd_cas_nxt : in std_logic;
    sd_we_nxt  : in std_logic;
    sd_ba_nxt  : in std_logic_vector(1 downto 0);
    sd_a_nxt   : in std_logic_vector(12 downto 0);

    wren_nxt  : in std_logic;
    wdata_nxt : in std_logic_vector(31 downto 0);

    rden_nxt : in  std_logic;
    rdata    : out std_logic_vector(31 downto 0);
    rstb     : out std_logic;

    sd_ck_p : out   std_logic;
    sd_ck_n : out   std_logic;
    sd_cke  : out   std_logic;
    sd_cs   : out   std_logic;
    sd_ras  : out   std_logic;
    sd_cas  : out   std_logic;
    sd_we   : out   std_logic;
    sd_ba   : out   std_logic_vector(1 downto 0);
    sd_a    : out   std_logic_vector(12 downto 0);
    sd_ldqs : out   std_logic;
    sd_udqs : out   std_logic;
    sd_dq   : inout std_logic_vector(15 downto 0));

end sdram_ctrl_phy_s3esk;