PoC.mem.ocram.sp

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Inferring / instantiating single port memory, with:

  • single clock, clock enable,
  • 1 read/write port.

Command Truth Table:

ce we Command
0 X No operation
1 0 Read from memory
1 1 Write to memory

Both reading and writing are synchronous to the rising-edge of the clock. Thus, when reading, the memory data will be outputted after the clock edge, i.e, in the following clock cycle.

When writing data, the read output will output the new data (in the following clock cycle) which is aka. “write-first behavior”. This behavior also applies to Altera M20K memory blocks as described in the Altera: “Stratix 5 Device Handbook” (S5-5V1). The documentation in the Altera: “Embedded Memory User Guide” (UG-01068) is wrong.

Entity Declaration:

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entity ocram_sp is
  generic (
    A_BITS    : positive;                             -- number of address bits
    D_BITS    : positive;                             -- number of data bits
    FILENAME  : string    := ""                       -- file-name for RAM initialization
  );
  port (
    clk : in  std_logic;                              -- clock
    ce  : in  std_logic;                              -- clock enable
    we  : in  std_logic;                              -- write enable
    a  : in unsigned(A_BITS-1 downto 0);              -- address
    d  : in std_logic_vector(D_BITS-1 downto 0);      -- write data
    q  : out std_logic_vector(D_BITS-1 downto 0)      -- read output
  );
end entity;