New in 1.x (upcoming)

Already documented changes are available on the release branch at GitHub.

• VHDL common packages
• VHDL Simulation helpers
• New Entities
  • PoC.mem.ocram.sdp_wf
  • PoC.mem.ocram.tdp_wf
  • PoC.cache.par2
  • PoC.cache.cpu
  • PoC.cache.mem
  • Simulation helper PoC.mem.ocram.tdp_sim
• Updated Entities
  • Interface of PoC.cache.tagunit_par changed slightly.
  • New port “write-mask” in PoC.mem.ddr3.mem2mig_adapter_Series7.
  • New port “write-mask” in PoC.mem.ddr2.mem2mig_adapter_Spartan6.
  • Fixed IP:dstruct_deque
• New Testbenches
  • Testbench for PoC.mem.ocram.sdp_wf
  • Testbench for PoC.mem.ocram.tdp_wf
  • Testbench for PoC.cache.par2
  • Testbench for PoC.cache.cpu
  • Testbench for PoC.cache.mem
• Updated Testbenches
  • Testbench for PoC.mem.ocram.sdp
  • Testbench for PoC.mem.ocram.esdp
  • Testbench for PoC.mem.ocram.tdp
  • Testbench for PoC.sort.sortnet.BitonicSort
  • Testbench for PoC.sort.sortnet.OddEvenSort
  • Testbench for PoC.sort.sortnet.OddEvenMergeSort
• New Constraints
• Updated Constraints
• Shipped Tool and Helper Scripts
• Python Infrastructure
  • Common changes
  • All Simulators
  • Aldec Active-HDL
  • GHDL
  • Mentor QuestaSim
  • Xilinx ISE Simulator
  • Xilinx Vivado Simulator
  • All Compilers
  • Altera Quartus Synthesis
  • Lattice Diamond (LSE)
  • Xilinx ISE (XST)
  • Xilinx ISE Core Generator
  • Xilinx Vivado Synthesis
• Continuous Integration
  • Implemented a simple Python infrastructe test on AppVeyor
• Documentation
  • Improved PDF rendering