# PoC.fifo.ic_got¶

Independent clocks meens that read and write clock are unrelated.

This implementation uses dedicated block RAM for storing data.

First-word-fall-through (FWFT) mode is implemented, so data can be read out as soon as valid goes high. After the data has been captured, then the signal got must be asserted.

Synchronous reset is used. Both resets may overlap.

DATA_REG (=true) is a hint, that distributed memory or registers should be used as data storage. The actual memory type depends on the device architecture. See implementation for details.

*STATE_*_BITS defines the granularity of the fill state indicator *state_*. fstate_rd is associated with the read clock domain and outputs the guaranteed number of words available in the FIFO. estate_wr is associated with the write clock domain and outputs the number of words that is guaranteed to be accepted by the FIFO without a capacity overflow. Note that both these indicators cannot replace the full or valid outputs as they may be implemented as giving pessimistic bounds that are minimally off the true fill state.

If a fill state is not of interest, set *STATE_*_BITS = 0.

fstate_rd and estate_wr are combinatorial outputs and include an address comparator (subtractor) in their path.

Examples: - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full

fstate_rd == 1 => 1/2 full (half full)
• FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full
fstate_rd == 1 => 1/4 full fstate_rd == 2 => 2/4 full fstate_rd == 3 => 3/4 full

Entity Declaration:

  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 entity fifo_ic_got is generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Write Interface clk_wr : in std_logic; rst_wr : in std_logic; put : in std_logic; din : in std_logic_vector(D_BITS-1 downto 0); full : out std_logic; estate_wr : out std_logic_vector(imax(ESTATE_WR_BITS-1, 0) downto 0); -- Read Interface clk_rd : in std_logic; rst_rd : in std_logic; got : in std_logic; valid : out std_logic; dout : out std_logic_vector(D_BITS-1 downto 0); fstate_rd : out std_logic_vector(imax(FSTATE_RD_BITS-1, 0) downto 0) ); end entity fifo_ic_got;